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Posted December 14, 2022

STAC Report: STAC-ML on Myrtle.ai VOLLO

First STAC-ML project using FPGAs as accelerators

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  • SUT ID: MRTL221125
  • STAC-ML

STAC-ML™ Pack for Myrtle.ai VOLLO™ with 4 x BittWare IA-840f (Intel® Agilex™ AGF027 FPGA) Cards in a BittWare TeraBox™ 1402B Server

Post date: 
Wednesday, December 14, 2022 - 09:55
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CITICSF

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GU Equity Partners, llc

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DZ7 TELECOMUNICACOES LTDA

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Sumo Futures

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EXA Infrastructure

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Andres Arcia-Moret

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self

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Advancing open source in FPGA

At the 19 October 2022 STAC Summit in New York, our panelists discussed "Low-latency market integration: Time to rethink buy-vs-build?". Panelists were:

  • Todd Strader, FPGA Engineer, Hudson River Trading
  • Stephen Kopec, North America, Data Center FAE Manager, AMD
  • Darrin Machay, Principal Engineer, Arista Networks

The following vendors gave short presentations before the panel discussion:

  "Open-Source Pros & Cons in the FPGA Development Flow"
    Stephen Kopec, North America, Data Center FAE Manager, AMD
  "Low-latency layer 3 and FPGAs"
    Darrin Machay, Principal Engineer, Arista Networks

 

Watch the panel discussion below.

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