Show me some love: Improving the FPGA “Engineer Experience”
At the 17 October 2024 STAC Summit in New York, our panelists discussed 'Show me some love: Improving the FPGA “Engineer Experience”'. Panelists were:
- Ben Maron, Head of Hardware Engineering, Hudson River Trading
- Rajiv Perera, Director of Hardware and HFT Engineering, MA Capital
- Michael Gorbovitski, Executive Director, Morgan Stanley
- Lakshmi Aiyer, Director, Sr. FPGA ULL Developer, UBS Financial Services
- Matthew Certosimo, Data Center FPGA Field Application Engineer, AMD
- Vijay Akkaraju, Application Engineer Architect, System Verification Group (“SVG”) AE, Cadence
Watch the panel discussion below.
Related Event
NOTE: Some or all of the content on this page and its attachment(s) were supplied by a party other than STAC. STAC does not endorse the content. No performance claims are supported by STAC except those found in an official STAC Report of results audited by STAC.