Vault report: STAC-M1 results of SR Labs MIPS on Everest and Westmere processors

Audited STAC-M1 Benchmarks of SR Labs MIPS Market Data Line Handler 3.7.0 with TVITCH 4.1 on two different Intel servers.

10 October 2011 - New York

SR Labs has completed testing of the SR Labs Market Data In Process System (MIPS) market data feed handling software using the STAC-M1 v2.0 specifications on two of the latest Intel processors, the X5687 ("Westmere") and the X5698 ("Everest"), and STAC has audited the results. This testing is a followup to the previous comparison report released in June, adding more test sequences relevant to embedded solutions. The results have been placed in the STAC Vault.

In these tests, the two “stacks under test” were identical except for the processors:

• SR Labs MIPS In-Process Market Data Line Handler 3.7.0 for TVITCH 4.1
• CentOS 5.5, 64-bit
• IBM x3650 M3 Server
• Myricom 10G-PCIE2-8B2-2S NIC with DBL 1.0.3
• Processor:
SUT ID MIPS110907: 2 x quad core Intel Xeon X5687 3.60 GHz (“Westmere”)
SUT ID MIPS110922: 2 x dual core Intel Xeon X5698 4.40 GHz (“Everest”)

The test harness used TS-Associates’ TipOff and Simena F16 Fiber Optic Tap for wire-based observation, alon with TS-Associates’ Application Tap cards for precise in-process observation. A Symmetricom SyncServer S350 was the time source for the harness.

Qualified members of the STAC Benchmark Council can access the reports below:

• Westmere Report
• Everest Report