Vault Report: Xilinx Alveo U250 FPGA under STAC-A2 (derivatives risk)

First FPGA implementation of STAC-A2 benchmarks

23 July 2020

Xilinx recently performed STAC-A2 Benchmark tests on a stack consisting of Vitis 19.2 with 8 x Xilinx Alveo U250 accelerator cards in a BOXX GX8-M Server and submitted the results to the STAC Vault.

STAC-A2 is the technology benchmark standard based on financial market risk analysis. Designed by quants and technologists from some of the world's largest banks, STAC-A2 reports the performance, scaling, quality, and resource efficiency of any technology stack that is able to handle the workload (Monte Carlo estimation of Heston-based Greeks for a path-dependent, multi-asset option with early exercise).

These STAC-A2 tests were performed using a Xilinx-authored STAC Pack. The STAC Pack was written using Xilinx Vitis Unified Software Platform, which includes a core development kit to build accelerated applications, a set of hardware-accelerated open-source libraries optimized for Xilinx hardware platforms, and plug-in domain-specific development environments enabling development directly in familiar, higher-level frameworks.

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