STAC Report: STAC-A2 (derivatives risk) on 8 x Alveo U250 FPGA cards in a BOXX GX8-M

First ever STAC-A2 audit results from FPGA accelerator boards

20 April 2021

STAC recently performed STAC-A2 Benchmark tests on a stack consisting of Xilinx Vitis Unified Software Platform 2020.2 with eight Xilinx Alveo U250 FPGA cards in a BOXX GX8-M server.

The STAC Report is now available here.

STAC-A2 is the technology benchmark standard based on financial market risk analysis. Designed by quants and technologists from some of the world's largest banks, STAC-A2 reports the performance, scaling, quality, and resource efficiency of any technology stack that is able to handle the workload (Monte Carlo estimation of Heston-based Greeks for a path-dependent, multi-asset option with early exercise).

Xilinx wished to highlight several results from this report:

• Compared to the most recently benchmarked solution using CPUs (SUT ID INTC190903), this system:
• Had a 1.48x speed-up in the cold run of the baseline problem size (STAC-A2.β2.GREEKS.TIME.COLD)
• Was 14.1% faster in cold runs of the large problem size (STAC-A2.β2.GREEKS.10-100k-1260.TIME.COLD)
• Had 20% higher maximum paths (STAC-A2.β2.GREEKS.MAX_PATHS)

• Compared to the most recently benchmarked solution using GPUs (SUT ID NVDA200909), this system:
• Was within 11.3% in the cold run of the baseline problem size (STAC-A2.β2.GREEKS.TIME.COLD)
• Was within 31.9% in the cold runs of the large problem size (STAC-A2.β2.GREEKS.10-100k-1260.TIME.COLD)

For details, please see the report at the link above. Premium subscribers have access to the code used in this project as well as the micro-detailed configuration information for the solution. To learn about subscription options, please contact us.