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10GbE and 25GbE Low-latency SerDes PMAs for ASIC Implementation

Jeff Lumish, Director of Digital Design, Silicon Creations, presented this at the 19 May 2022 STAC Summit in London.

Download the slides below.

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STAC-Summit-19-May-2022-silicon-creations.pdf	726.64 KB

Related Event

STAC Summit, 19 May 2022, London

NOTE: Some or all of the content on this page and its attachment(s) were supplied by a party other than STAC. STAC does not endorse the content. No performance claims are supported by STAC except those found in an official STAC Report of results audited by STAC.