STAC event content involving Cadence Design Systems

Show me some love: Improving the FPGA “Engineer Experience”

At the 17 October 2024 STAC Summit in New York, our panelists discussed 'Show me some love: Improving the FPGA “Engineer Experience”'. Panelists were:

Ben Maron, Head of Hardware Engineering, Hudson River Trading
Rajiv Perera, Director of Hardware and HFT Engineering, MA Capital
Michael Gorbovitski, Executive Director, Morgan Stanley
Lakshmi Aiyer, Director, Sr. FPGA ULL Developer, UBS Financial Services
Matthew Certosimo, Data Center FPGA Field Application Engineer, AMD
Vijay Akkaraju, Application Engineer Architect, System Verification Group (“SVG”) AE, Cadence

Watch the panel discussion below.

Deploy HFT Accelerators Faster with COFE!

Vijay Akkaraju, Application Engineer Architect, System Verification Group (“SVG”) AE, Cadence, presented this at the 17 October 2024 STAC Summit in New York.

Watch the video below:

Download the slides below.

Staying cool at speed: Adding 25G to HFT accelerators

Dr. Lawrence Der, Application Engineering Director, Cadence, presented this at the 14 May 2024 STAC Summit in New York.

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Download the slides below.

Talent shortages in hardware verification: Can ML plug the gaps?

Adam Sherer, Verification Technology Executive, Cadence, presented this at the 19 October 2023 STAC Summit in New York.

Watch the video below.

Download the slides below.

FPGAs beyond ultra-low latency?

At the 31 May 2023 STAC Summit in New York, our panelists discussed "FPGAs beyond ultra-low latency?". Panelists were:

The following vendors gave short presentations before the panel discussion:

	"FPGA Hardware Acceleration in Electronic Trading, AI, and Data Analytics" Matt Certosimo, Data Center FPGA Field Application Engineer, AMD
	"The Edge of the Edge: PCB Latency in Trading Reaction Time" Adam Sherer, Verification Technology Executive, Cadence Design Systems